1. Field of the Invention
The present invention relates to an apparatus, method, computer program and mobile terminal for processing information appropriately for use as mobile devices such as a cellular phone, a personal handyphone system (PHS) phone, a personal digital assistant (PDA), or a notebook personal computer.
2. Description of the Related Art
Basic data processing functions of computer systems include fetching (data acquisition), decoding (analysis), and execution. With today's advanced central processing units (CPUs), decoding and execution are performed at a high speed. But the fetching process still remains to be a factor delaying data processing at any layer of the computer system. More specifically, the factors affecting the data processing speed include a delay in data fetching between the CPU and memory (von Neumann bottleneck), a delay in data fetching between a personal computer and an external storage, a delay in data fetching between a server and a client terminal, etc.
A reduction in the data processing speed is improved by pre-fetching data expected to be processed later onto a cache memory in accordance with a predetermined algorithm. The cache memory typically permits high-speed accessing. The data typically has temporal locality and spatial locality. Whenever data is used, the same data is mostly likely to be used again in the near future (temporal locality). Whenever data at an address is to be processed, data to be processed next is mostly likely present at an address in the vicinity of the first address (spatial locality).
To process data in accordance with an algorithm based on the temporal locality, the CPU stores the processed data onto a cache memory, and reads the data from the cache memory for processing when the processing of the same data is requested next time. High speed processing is achieved in this way.
To process data in accordance with an algorithm based on the spatial locality, the CPU stores, on the cache memory, together with the data to be currently processed, data at a nearby address highly likely to be processed next. The CPU is thus prepared for a next data processing request.
As related cache memory techniques, Japanese Unexamined Patent Application Publication No. 2004-118305 discloses a cache memory controller and Japanese Unexamined Patent Application Publication No. 2005-018441 discloses a memory device.